Inner Loop Code Generation for Coarse-Grained Reconfigurable Instruction Set Processors
نویسندگان
چکیده
Reconfigurable instruction set processors can potentially reduce the power consumption of high performance multimedia applications by fusing the concept of a reconfigurable array with a programmable processor. In particular, VLIW processors with coarse-grained reconfigurable functional units are specially suited to low power multimedia applications. Code generation for this type of processors is a critical issue, since assembly programming is extremely difficult due to the complexity of the hardware. This paper describes a new code generation technique for this type of processors that optimizes execution speed. The technique, based on software pipelining, combines instruction creation and instruction scheduling in the same algorithm. In this manner, the code generation algorithm provides maximum utilization of resources by simultaneously using the fixed functional units and the processing elements inside the reconfigurable unit.
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